1. Field of the Invention
The invention relates in general to an electrostatic discharge (ESD) protection device and a method thereof, and more particularly to an ESD protection device for a pad and a method thereof.
2. Description of the Related Art
The electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects with the accumulation of the electrostatic charges. The ESD occurs for an extremely short period of time, which is only within the level of several nano-seconds (ns). A very high current is generated in the ESD event, and the value of the current is usually several amperes. Consequently, once the current generated by the ESD flows through a semiconductor integrated circuit, the semiconductor integrated circuit is usually damaged. Thus, the ESD protection device between power lines has to provide a discharge path to prevent the semiconductor integrated circuit from being damaged when the high-voltage electrostatic charges are generated in the semiconductor integrated circuit.
FIG. 1A (Prior Art) is a schematic illustration showing a conventional snapback element 100. As shown in FIG. 1A, the snapback element 100, such as an N-type metal oxidation semiconductor (NMOS) transistor, has a drain electrically connected to a pad 10, and a gate and a source coupled to each other and to a reference potential, such as a ground potential. Two factors of the snapback element 100 associated with the ESD event include a triggering voltage and a holding voltage. In general, the performance of the ESD is better as the triggering voltage and the holding voltage become lower.
FIG. 1B (prior art) shows a current-voltage characteristic curve of the snapback element 100. As shown in FIG. 1B, when a high voltage A is inputted, the snapback element 100 is charged until the voltage level of the snapback element 100 reaches a triggering voltage C and then snaps back to a holding voltage D. In a normal high-voltage operation, however, if the snapback element 100 is sometimes triggered, the snapback element 100 is damaged because the holding voltage D is lower than the normal input high voltage. Thus, the manufacturer and the designer have tried very hard to provide an ESD protection device, which has the higher triggering voltage and the higher holding voltage under the operation voltage of the normally high voltage, and has the lower triggering voltage and the lower holding voltage under the ESD event.
FIG. 3 of U.S. Pat. No. 6,965,504 is a circuit diagram showing a conventional ESD protection device. The ESD protection device additionally includes a P-type guard ring and an N-type guard ring respectively disposed outside an adjusting circuit and a snapback element, and a guard ring control circuit is provided to control the P-type guard ring and the N-type guard ring. Thus, the P-type guard ring and the N-type guard ring collects the excess positive and negative charges in the normal operation mode, and the ESD protection device thus has the higher triggering voltage and the higher holding voltage. In the ESD mode, the P-type guard ring and the N-type guard ring do not collect the excess positive and negative charges, so the ESD protection device has the lower triggering voltage and the lower holding voltage.
However, adding the guard ring and the control circuit to the ESD protection circuit may enlarge the area of the circuit in the manufacturing processes and thus increase the cost. Thus, it is an important problem to be solved to provide an ESD protection device capable of having the higher triggering voltage and the higher holding voltage during the normal operation and having the lower triggering voltage and the lower holding voltage during the ESD without greatly enlarging the circuit area.